When a digital logic signal or clock signal is coupled from a sending circuit to a receiving circuit, the signal can be corrupted by distortion and noise, often referred to as glitches. A glitch can cause the signal to cross the threshold between a logic zero and a logic one, causing the value of the signal to be misinterpreted by the receiving circuit.
Such glitches, including double clocking errors, may occur on the input clock of certain memory devices when data and address lines are switching at high speeds. Typically, the input clock is stable during a logic one or logic zero, but is particular susceptible to noise during the transition from high to low or low to high. Such devices may include Micro SD memory devices, SD memory devices, iNAND memory devices, and other memory devices, available from SanDisk Corp. of California. These memory devices may be susceptible to double clocking and noise glitches because of the very small space in which the memory circuits are packaged. Very small or tight package designs often cannot provide sufficient space in which to fabricate or install capacitors, or for placing shielding on the package substrate.
Memory devices, such as for example, the flash memory devices and other memory devices mentioned above, have been widely adopted for use in consumer products. Flash memory may be found in different forms, for example in the form of a portable memory card that can be carried between host devices or as a solid state drive (SSD) embedded in a host device. Two general memory cell architectures found in flash memory include NOR and NAND. In a typical NOR architecture, memory cells are connected between adjacent bit line source and drain diffusions that extend in a column direction with control gates connected to word lines extending along rows of cells. A memory cell includes at least one storage element positioned over at least a portion of the cell channel region between the source and drain. A programmed level of charge on the storage elements thus controls an operating characteristic of the cells, which can then be read by applying appropriate voltages to the addressed memory cells.
A typical NAND architecture utilizes strings of more than two series-connected memory cells, such as 16 or 32, connected along with one or more select transistors between individual bit lines and a reference potential to form columns of cells. Word lines extend across cells within many of these columns. An individual cell within a column is read and verified during programming by causing the remaining cells in the string to be turned on so that the current flowing through a string is dependent upon the level of charge stored in the addressed cell.
NAND flash memory can be fabricated in the form of single-level cell flash memory, also known as SLC or binary flash, where each cell stores one bit of binary information. NAND flash memory can also be fabricated to store multiple states per cell so that two or more bits of binary information may be stored. This higher storage density flash memory is known as multi-level cell or MLC flash. MLC flash memory can provide higher density storage and reduce the costs associated with the memory. The higher density storage potential of MLC flash tends to have the drawback of less durability than SLC flash in terms of the number write/erase cycles a cell can handle before it wears out. MLC can also have slower read and write rates than the more expensive and typically more durable SLC flash memory. Memory devices, such as SSDs, may include both types of memory.
With respect to memory circuits and devices, conventional de-glitch circuits typically remove glitches from a digital input signal by requiring a change in the input signal to persist for at least a predetermined time period, referred to as the de-glitching period or “glitch width,” before the change is propagated to the output of the glitch filter. However, this type of glitch filter has the disadvantage of delaying the input signal by a time greater than or equal to the predetermined de-glitching period. Some digital logic circuits will not operate correctly if their input signals are subject to such delay.
Some known glitch filters use simple delay lines and combinatorial logic to filter the glitches. The main disadvantage of this approach is that the delay line is constant and sensitive to process, voltage, and temperature variations. Other known glitch filters use a Schmidt trigger with a predefined hysteresis value. However, Schmidt triggers cannot filter high amplitude glitches beyond its threshold. Still other methods use sampling by high speed clock. However, this approach is not applicable for high speed input signals, as the sampling clock must be at least ten times faster than input signal.
Known delay lines have been used to provide some degree of glitch filtering. However, due to the high frequencies of input signals and conservative duty-cycle requirements of certain memory devices, simple delay lines are not adequate because of the dependency on the silicon manufacturing process, operating voltage and temperature.
Another deficiency of known glitch filters is that they do not ensure high accuracy of the “glitch width” (pulse width to be filtered). Further, some memory devices require that the “glitch width” parameters change during operation, depending on selected speed mode of the memory device, and such simple glitch filters do not provide a selectable glitch width.